Integrated circuits, also referred to as “chips”, must have a multi-layer interconnection structure, including a plurality of interwoven conductive lines to electrically connect elements in the semiconductor layers. Different techniques are used to build this structure, depending on whether the chip is aluminum-based or copper-based. A problem that is faced in constructing an aluminum interconnection structure is varying dielectric thickness, whereas for a copper interconnection structure varying copper thickness can be a problem.
Copper-based chips are produced, in part, using a damascene or dual-damascene process. In this process, the underlying dielectric material layer is patterned with open trenches that are created in the desired locations of the prospective conductive lines. A thick coating of copper that significantly overfills the trenches is deposited on the dielectric material, and chemical-mechanical planarization or polishing (CMP) is used to remove the copper to the level of the top of the dielectric insulating layer.
With successive layers of insulator and copper, the multilayer (5-10 metal layers or more) interconnection structure is created. Unfortunately, it has not yet been possible to match the rate at which copper is removed during CMP with the rate at which the dielectric material is removed, with the copper generally being removed more rapidly. Consequently, an area with more embedded copper structures will generally be removed more quickly, potentially leading to an uneven surface and uneven copper structure thickness. In turn, this could affect performance in an unpredictable manner, because the electrical characteristics of the copper structures are affected by their thicknesses.
With respect to the CMP process, ideally all of the dielectric would be uniformly exposed at the same moment, and the process would be brought to a stop at that moment. Sometimes, however, the dielectric layer is exposed in one region, but not exposed in another. The CMP process must continue until the dielectric is exposed across all regions, causing some copper to be recessed relative to the dielectric (“dishing”, or local “step height”), and removal of dielectric in an area having a high density of conductive lines, versus areas having few or no conductive lines (“erosion”, or global “step height”). For copper-based chip fabrication, processes have been developed that remove the dielectric more quickly than the copper, to minimize the above described effects.
For aluminum-based chips, aluminum structures are constructed first, and then covered with dielectric. Typically, however, the top of the dielectric layer is not flat after the process of covering the aluminum structures is complete. Although CMP is used to create a flat top surface, the top surface of the dielectric will tend to be lower where it is covering a low density of aluminum structure, and higher where a high density of aluminum structure is covered. This variation is undesirable and dummy or “fill” elements are typically added to a layout to minimize this effect. Unlike the situation with respect to a copper-based chip, however, metal structure thicknesses are not affected. For both aluminum- and copper-based chips, the fill elements can be either “floating”, i.e., having no conducting path to either a power or a ground supply, or “tied”, i.e., having an electrical connection directly to power or ground. Floating fill in general has less capacitance impact on nearby signal wires than does tied fill. On the other hand, tied fill is a superior choice for control of crosstalk noise or loop inductance.
Complicating this situation is the fact that modern-day chip design is increasingly becoming a process in which intellectual property (IP) in the form of circuit layouts from various suppliers is integrated together by an IP integrator. In some instances the IP integrator is one part of a large corporate entity, and the IP supplier is another. In other instances the IP integrator purchases IP from a separate vendor or vendors. The resultant integrated layout is then fabricated at a foundry, which may or may not be owned by the IP integrator.
Frequently, for a particular piece of IP, non-functional metal fill elements will have been added to the layout, thereby increasing the uniformity of the density of the metal pattern. This, in turn, prevents unevenness that could be caused by the CMP process, as explained above. The metal density of a first piece of IP may not, and frequently does not, however, match that of a second, prospectively neighboring piece of IP. The foundries have rules for the minimum and maximum density of the metal patterns, and the IP vendors typically design their pieces with “max fill” so as to approximate the upper metal pattern density limit or “min fill” so as to approximate the lower metal density limit. While we use the term “density” for pedagogic purposes in this discussion, it should be noted that fill elements ultimately are used to increase the uniformity of the CMP process outcome itself. Thus, “density” may be viewed as a proxy for post-CMP thickness or step height, and in this context “max fill” denotes a solution with maximum amount of inserted fill subject to a thickness variation constraint, while “min fill” denotes a solution with minimum inserted fill subject to a thickness variation constraint.
Accordingly, the IP integrator is faced with a troublesome problem of matching metal pattern densities between pieces of IP or between a piece of IP and an adjacent custom design. This is complicated by restrictions generally placed on the removal of metal fill elements by the IP providers, who will typically not guarantee the functionality of a piece of IP from which fill elements have been removed. Although fill elements may typically be added to the less dense metal pattern, this is done by the designer with some uncertainty as to the effect of these additions.